IS42S16320B-7TL SDRAM 64Mb Density 166MHz Speed 3.3V Operation
16Mx16 Organization LVTTL Interface Industrial Temp (-40°C~85°C)
Compact TSOP-II Package High Reliability
FEATURES
• Clock frequency: 166, 143, 133 MHz
• Fully synchronous; all signals referenced to a positive clock
edge
• Internal bank for hiding row access/precharge
• Power supply
Vdd Vddq
IS42/45S16320B 3.3V 3.3V
IS42S86400B 3.3V 3.3V
• LVTTL interface
• Programmable burst length – (1, 2, 4, 8, full page)
• Programmable burst sequence: Sequential/Interleave
• Auto Refresh (CBR)
• Self Refresh
• 8K refresh cycles every 16ms (A2 grade) or 64 ms (Commercial,
Industrial, A1 grade)
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write operations
capability
• Burst termination by burst stop and precharge command
• Available in 54-pin TSOP-II and 54-ball W-BGA (x16 only)
• Operating Temperature Range:
Commercial: 0oC to +70oC
Industrial: -40oC to +85oC
Automotive, A1: -40oC to +85oC
Automotive, A2: -40oC to +105oC
OVERVIEW
ISSI's 512Mb Synchronous DRAM achieves high-speed data transfer
using pipeline architecture. All inputs and outputs signals refer
to the rising edge of the clock input. The 512Mb SDRAM is organized
as follows.
DEVICE OVERVIEW
The 512Mb SDRAM is a high speed CMOS, dynamic random-access memory
designed to operate in 3.3V Vdd and 3.3V Vddq memory systems
containing 536,870,912 bits. Internally configured as a quad-bank
DRAM with a synchronous interface. Each 134,217,728-bit bank is or
ganized as 8,192 rows by 1024 columns by 16 bits. Each of the x8's
134,217,728-bit banks is organized as 8,192 rows by 2048 columns by
8 bits.
The 512Mb SDRAM includes an AUTO REFRESH MODE, and a power-saving,
power-down mode. All signals are registered on the positive edge of
the clock signal, CLK. All inputs and outputs are LVTTL compatible.
The 512Mb SDRAM has the ability to synchronously burst data at a
high data rate with automatic column-address generation, the
ability to interleave between internal banks to hide precharge time
and the capability to randomly change column addresses on each
clock cycle during burst access.
A self-timed row precharge initiated at the end of the burst
sequence is available with the AUTO PRECHARGE function enabled.
Precharge one bank while accessing one of the other three banks
will hide the precharge cycles and provide seamless, high-speed,
random-access operation.
SDRAM read and write accesses are burst oriented starting at a
selected location and continuing for a programmed number of
locations in a programmed sequence. The registration of an ACTIVE
command begins accesses, followed by a READ or WRITE command. The
ACTIVE command in conjunction with address bits registered are used
to select the bank and row to be accessed (BA0, BA1 select the
bank; A0-A12 select the row). The READ or WRITE commands in
conjunction with address bits registered are used to select the
starting column location for the burst access.
Programmable READ or WRITE burst lengths consist of 1, 2, 4 and 8
locations or full page, with a burst terminate option.
DESCRIPTION
The 512Mb SDRAMs are quad-bank DRAMs which operate at 3.3V and
include a synchronous interface (all signals are registered on the
positive edge of the clock signal, CLK). Each of the
134,217,728-bit banks is organized as 8,192 rows by 1024 columns by
16 bits or 8192 rows by 2048 columns by 8bits.
Read and write accesses to the SDRAM are burst oriented; accesses
start at a selected location and continue for a programmed number
of locations in a programmed sequence. Accesses begin with the
registration of an ACTIVE command which is then followed by a READ
or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed
(BA0 and BA1 select the bank, A0 A12 select the row). The address
bits A0-A9 (x16); A0-A9, A11 (x8) registered coincident with the
READ or WRITE command are used to select the starting column
location for the burst access.
Prior to normal operation, the SDRAM must be initial ized. The
following sections provide detailed information covering device
initialization, register definition, command descriptions and
device operation.
INFORMATION
Category | | |
Mfr | | |
Series | | |
Packaging | | |
Part Status | | |
DigiKey Programmable | | |
Memory Type | | |
Memory Format | | |
Technology | | |
Memory Size | | |
Memory Organization | | |
Memory Interface | | |
Clock Frequency | | |
Write Cycle Time - Word, Page | | |
Access Time | | |
Voltage - Supply | | |
Operating Temperature | | |
Mounting Type | | |
Package / Case | | |
Supplier Device Package | | |
Base Product Number | |
Drawing
Our advantage :
- High quality products --- our offers are 100% new and original,
ROHS
- Competitive price --- good Purchase channels with good price.
- Professional service --- strict quality testing before the
shipment, and perfect after-sales service after the purchase.
- Adequate inventory --- With the support of our strong Purchasing
team,
- Fast delivery --- we will ship the goods within 1-3 working days
after the payment confirmed.
be sure to meet your need for all kinds of components. ^_^
Product List
Supply a Series of Electronic Components, full range of
semiconductors, active & passive Components.We can help you to get
all for bom of the PCB,IN a word, you can get one-stop solution
here,
The offers including:
Integrated Circuit, Memory ICs, Diode, Transistor , Capacitor,
Resistor, Varistor, Fuse, Trimmer & Potentiometer, Transformer,
Battery, Cable, Relay, Switch, Connector, Terminal Block, Crystal &
Oscillator, Inductor, Sensor, Transformer, IGBT Driver, LED,LCD,
Convertor, PCB (Printed Circuit Board),PCBA (PCB Assembly)
Strong in Brand:
Microchip, MAX, AD, TI, ATMEL, ST, ON, NS, Intersil, Winbond,
Vishay, ISSI, Infineon, NEC, FAIRCHILD, OMRON,YAGEO, TDK, etc
